Invention Grant
US08195856B2 I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
有权
用于DFPS的I / O和存储器总线系统以及具有二维或多维可编程单元架构的单元
- Patent Title: I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
- Patent Title (中): 用于DFPS的I / O和存储器总线系统以及具有二维或多维可编程单元架构的单元
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Application No.: US12840742Application Date: 2010-07-21
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Publication No.: US08195856B2Publication Date: 2012-06-05
- Inventor: Martin Vorbach , Robert Münch
- Applicant: Martin Vorbach , Robert Münch
- Agency: Kenyon & Kenyon LLP
- Priority: DE19654595 19961220
- Main IPC: G06F15/76
- IPC: G06F15/76
Abstract:
A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).
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