Invention Grant
- Patent Title: Systolic array
- Patent Title (中): 收缩阵列
-
Application No.: US11878058Application Date: 2007-07-20
-
Publication No.: US08195733B2Publication Date: 2012-06-05
- Inventor: Katsutoshi Seki
- Applicant: Katsutoshi Seki
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Foley & Lardner LLP
- Priority: JP2006-199682 20060721
- Main IPC: G06F7/32
- IPC: G06F7/32 ; G06F7/38

Abstract:
Disclosed is a one-dimensional MFA systolic array for matrix computation using an MFA (modified Faddeeva algorithm), in which downward square MFA array processing and upward square MFA array processing are mapped to a one-dimensional array in horizontal directions, respectively. In each PE in the one-dimensional array, downward and upward MFA matrix calculations for two threads are executed. An input and an output are provided for each of PEs at both ends of the one-dimensional array.
Public/Granted literature
- US20080028015A1 Systolic array Public/Granted day:2008-01-31
Information query