A system can include a bus proxy comprising a primary slave coupled to a processor via a bus. The bus proxy system can include a hardware co-simulation interface disposed within the programmable IC and coupled to the bus proxy. The hardware co-simulation interface can buffer simulation data from the bus proxy and the host processing system. The bus proxy can include a secondary slave executing with a host processing system that reads data from, and writes data to, the hardware co-simulation interface, and communicates with at least one high level modeling system (HLMS) block executing within the host processing system. The primary slave can exert a slave wait signal on the bus responsive to detecting a bus request from the processor specifying an address corresponding to the HLMS block within the host processing system.