Invention Grant
US08194854B2 Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation
有权
用于在并行运行模式下优化先进加密标准（AES）加密和解密的方法和装置
- Patent Title: Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation
- Patent Title (中): 用于在并行运行模式下优化先进加密标准（AES）加密和解密的方法和装置
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Application No.: US12038071Application Date: 2008-02-27
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Publication No.: US08194854B2Publication Date: 2012-06-05
- Inventor: Shay Gueron , Amit Gradstein , Zeev Sperber
- Applicant: Shay Gueron , Amit Gradstein , Zeev Sperber
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H04L9/06
- IPC: H04L9/06 ; H04L9/00 ; H04L9/30 ; H04L9/28 ; H03K19/173 ; H04K1/04
Abstract:
The throughput of an encryption/decryption operation is increased in a system having a pipelined execution unit. Different independent encryptions (decryptions) of different data blocks may be performed in parallel by dispatching an AES round instruction in every cycle.
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