Various exemplary embodiments provide methods of controlling frame memory, memory control circuits, and image processing apparatuses including the memory control circuits. Data representing values of pixels constituting each of a plurality of frames are received in an order of the frames, and data representing values of pixels constituting a previous frame are read from the frame memory and data representing values of pixels constituting a next frame are written to the frame memory. By reading first data representing values of a portion of the pixels constituting the previous frame from the frame memory before receiving of data representing values of pixels constituting the next frame starts, a delay time before starting to output data representing values of pixels of the previous frame can be shortened.