Invention Grant
- Patent Title: All-digital phase-locked loop
- Patent Title (中): 全数字锁相环
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Application No.: US12202310Application Date: 2008-08-31
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Publication No.: US08193866B2Publication Date: 2012-06-05
- Inventor: Hsiang-Hui Chang
- Applicant: Hsiang-Hui Chang
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
- Assignee: Mediatek Inc.
- Current Assignee: Mediatek Inc.
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: H03L7/099
- IPC: H03L7/099

Abstract:
For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with only digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By modulating certain parameters within the ADPLL by following an all-pass frequency response, a loop gain of the ADPLL may be precisely modulated, and an available bandwidth of the ADPLL is also significantly broadened.
Public/Granted literature
- US20090096535A1 All-Digital Phase-Locked Loop Public/Granted day:2009-04-16
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