Invention Grant
- Patent Title: Push-pull output circuit
- Patent Title (中): 推挽输出电路
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Application No.: US12887312Application Date: 2010-09-21
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Publication No.: US08193863B2Publication Date: 2012-06-05
- Inventor: Hiroyuki Tsurumi
- Applicant: Hiroyuki Tsurumi
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Knobbe, Martens, Olson & Bear, LLP
- Priority: JP2010-000745 20100105
- Main IPC: H03F3/18
- IPC: H03F3/18

Abstract:
According to one embodiment, a first transistor is connected between a first power supply rail and an output unit. A second transistor is connected between the output unit and a second power supply rail. A gm amplifier includes an input unit and first and second output terminals and amplifies a difference between a signal input to the input unit and a reference voltage. First and second current mirror circuits are connected to be vertically stacked between the first rail and the first terminal as well as a gate of the second transistor. Third and fourth current mirror circuits are connected to be vertically stacked between the second rail and the second terminal as well as a gate of the first transistor. The gate of the first transistor is connected to the first and second circuits. The gate of the second transistor is connected to the third and fourth circuits.
Public/Granted literature
- US20110163809A1 PUSH-PULL OUTPUT CIRCUIT Public/Granted day:2011-07-07
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