Invention Grant
- Patent Title: Thru silicon enabled die stacking scheme
- Patent Title (中): 通过硅芯片堆叠方案
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Application No.: US13110144Application Date: 2011-05-18
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Publication No.: US08193093B2Publication Date: 2012-06-05
- Inventor: Satyendra Singh Chauhan
- Applicant: Satyendra Singh Chauhan
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Steven A. Shaw; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/48
Abstract:
A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die.
Public/Granted literature
- US20110250720A1 THRU SILICON ENABLED DIE STACKING SCHEME Public/Granted day:2011-10-13
Information query
IPC分类:
