Invention Grant
US08192919B2 Pattern forming method, semiconductor device manufacturing method and phase shift photomask having dummy gate patterns
失效
图案形成方法,半导体器件制造方法和具有虚拟栅极图案的相移光掩模
- Patent Title: Pattern forming method, semiconductor device manufacturing method and phase shift photomask having dummy gate patterns
- Patent Title (中): 图案形成方法,半导体器件制造方法和具有虚拟栅极图案的相移光掩模
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Application No.: US12801424Application Date: 2010-06-08
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Publication No.: US08192919B2Publication Date: 2012-06-05
- Inventor: Masashi Fujimoto
- Applicant: Masashi Fujimoto
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2005-078125 20050317
- Main IPC: H01L21/00
- IPC: H01L21/00 ; G03F1/00 ; G03C5/00

Abstract:
A method for forming a plurality of gate patterns in parallel with each other on a photoresist layer within a circuit block includes forming extension gate patterns on both ends of the gate patterns and on both ends of a dummy gate pattern of the circuit block to reach an edge of the circuit block, and performing a first photolithography process upon the photoresist layer by using a phase shift photomask having first and second openings whose difference in phase is π, the first and second openings alternating between the gate patterns including the extension gate patterns to form phase edges therein.
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