Invention Grant
US08171323B2 Integrated circuit with modular dynamic power optimization architecture
有权
具有模块化动态功耗优化架构的集成电路
- Patent Title: Integrated circuit with modular dynamic power optimization architecture
- Patent Title (中): 具有模块化动态功耗优化架构的集成电路
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Application No.: US12166065Application Date: 2008-07-01
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Publication No.: US08171323B2Publication Date: 2012-05-01
- Inventor: Vafa James Rakshani , Musaravakkam Samaram Krishnan
- Applicant: Vafa James Rakshani , Musaravakkam Samaram Krishnan
- Applicant Address: US CA Irvine
- Assignee: Broadcom Corporation
- Current Assignee: Broadcom Corporation
- Current Assignee Address: US CA Irvine
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: G06F1/00
- IPC: G06F1/00 ; G06F1/32

Abstract:
A system and method for regulating power consumption within an integrated circuit (IC) with a modular design. The IC is designed so that any one distinct functional module within the IC utilizes only transistors with a substantially same or similar critical voltage level, which may for example be the threshold voltage of the transistors. Consequently, the supply voltage delivered to each functional modules can be lowered to the minimum voltage necessary to enable the transistors within the module to operate. Similarly, modules within the IC may be designed with transistors which share a common value for a substrate bias voltage or a clock speed, or with a combination of common values for several electrical factors. In this way, it is possible to reduce power consumption by fine-tuning the voltages supplied to (or clock speeds driving) specific modules, in a way which is custom-tuned to each module.
Public/Granted literature
- US20100005328A1 Integrated Circuit with Modular Dynamic Power Optimization Architecture Public/Granted day:2010-01-07
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