Invention Grant
- Patent Title: Method and apparatus for reducing the processing rate of a chip-level equalization receiver
- Patent Title (中): 降低芯片级均衡接收机的处理速率的方法和装置
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Application No.: US13099674Application Date: 2011-05-03
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Publication No.: US08170083B2Publication Date: 2012-05-01
- Inventor: Kyle Jung-Lin Pan
- Applicant: Kyle Jung-Lin Pan
- Applicant Address: US DE Wilmington
- Assignee: InterDigital Technology Corporation
- Current Assignee: InterDigital Technology Corporation
- Current Assignee Address: US DE Wilmington
- Agency: Volpe and Koenig, P.C.
- Main IPC: H04B1/00
- IPC: H04B1/00 ; H04B7/10

Abstract:
A method and apparatus for reducing the processing rate when performing chip-level equalization (CLE) in a code division multiple access (CDMA) receiver which includes an equalizer filter. Signals received by at least one antenna of the receiver are sampled at M times the chip rate. Each sample stream is split into M sample data streams at the chip rate. Multipath combining is preferably performed on each split sample data stream. The sample data streams are then combined into one combined sample data stream at the chip rate. The equalizer filter performs equalization on the combined sample stream at the chip rate. Filter coefficients are adjusted by adding a correction term to the filter coefficients utilized by the equalizer filter for a previous iteration.
Public/Granted literature
- US20110206015A1 METHOD AND APPARATUS FOR REDUCING THE PROCESSING RATE OF A CHIP-LEVEL EQUALIZATION RECEIVER Public/Granted day:2011-08-25
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