Integrated circuit (20) comprising several different voltage rails (V5 to V1) and an on-chip ESD protection circuit. The ESD protection circuit comprises at least one group (21, 22, 23) of ESD clamp devices (C1-C4). The ESD clamp devices (C1-C4) are arranged in a ladder-configuration. This ladder-configuration is characterized in that there is one of the ESD clamp devices interposed between each of the power rails (V5 to V1) and the respective power rail having a next lower voltage. Due to this arrangement an ESD current path is defined between each one of the power rails and the power rail having the next lower voltage. The ESD clamp devices (C1-C4) are off under normal power operation of the integrated circuit (20).