The multiphase clock generation circuit includes a variable slew rate circuit and a phase interpolation circuit. In the variable slew rate circuit, the slew rate varies according to a first control signal. Two reference clocks having a phase difference of 90° from each other are supplied to the phase interpolation circuit via the variable slew rate circuit. The phase interpolation circuit interpolates the two reference clocks having a phase difference of 90° from each other according to a second control signal to thereby generate an output clock having an intermediate phase.