An integrated circuit includes a feedback controlled clock generating circuit, such as a DLL, PLL or other suitable circuit, that is operative to provide a feedback reference frequency signal based on a generated output clock signal. The integrated circuit also includes a programmable fine lock/unlock detection circuit that includes programmable static phase error sensitivity logic that senses phase error. The programmable static phase error sensitivity logic sets a phase lock sensitivity window used to determine a fine lock/unlock condition of the generated output clock signal. The programmable fine lock/unlock detection logic is also operative to generate a fine phase lock/unlock signal based on the set phase lock sensitivity window. The integrated circuit may also include a coarse lock detection circuit that generates a coarse lock signal based on a frequency unlock condition.