Invention Grant
US08169068B2 IO cell with multiple IO ports and related techniques for layout area saving
有权
具有多个IO端口的IO单元和相关技术，用于布局区域的保存
- Patent Title: IO cell with multiple IO ports and related techniques for layout area saving
- Patent Title (中): 具有多个IO端口的IO单元和相关技术，用于布局区域的保存
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Application No.: US12697582Application Date: 2010-02-01
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Publication No.: US08169068B2Publication Date: 2012-05-01
- Inventor: Jeng-Huang Wu , Hung-Yi Chang , Chun Huang
- Applicant: Jeng-Huang Wu , Hung-Yi Chang , Chun Huang
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
- Assignee: Faraday Technology Corp.
- Current Assignee: Faraday Technology Corp.
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
An IO cell with multiple IO ports and related techniques are provided. The IO cell has a plurality of IO ports for transmitting signal of a same IO pin, and each IO port corresponds to a predetermined region for containing an IO pad, wherein at least one of the plural predetermined regions of the plural IO ports partially overlaps with active circuit layout region of the IO cell. In a chip, if a given IO cell has a predetermined region of an IO port overlapping an IO pad location of another adjacent IO cell, then a predetermined region of another IO port is selected for implementing an IO pad of the given IO cell, such that the IO cells can be arranged more compactly for chip layout area saving.
Public/Granted literature
- US20100237509A1 IO CELL WITH MULTIPLE IO PORTS AND RELATED TECHNIQUES FOR LAYOUT AREA SAVING Public/Granted day:2010-09-23
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