Invention Grant
- Patent Title: Integrated circuit package for semiconductior devices with improved electric resistance and inductance
- Patent Title (中): 具有改善电阻和电感的半导体器件的集成电路封装
-
Application No.: US13114063Application Date: 2011-05-24
-
Publication No.: US08169062B2Publication Date: 2012-05-01
- Inventor: Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
- Applicant: Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee Address: US CA Sunnyvale
- Agency: Schein & Cai
- Agent Jingming Cai
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/48 ; H01L29/40 ; H01L23/52

Abstract:
A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
Public/Granted literature
- US20110221005A1 Integrated circuit package for semiconductior devices with improved electric resistance and inductance Public/Granted day:2011-09-15
Information query
IPC分类: