Invention Grant
- Patent Title: Substrate band gap engineered multi-gate pMOS devices
- Patent Title (中): 基板带隙工程多栅极pMOS器件
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Application No.: US12757917Application Date: 2010-04-09
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Publication No.: US08169027B2Publication Date: 2012-05-01
- Inventor: Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta
- Applicant: Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L29/66
- IPC: H01L29/66

Abstract:
A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.
Public/Granted literature
- US20100193840A1 SUBSTRATE BAND GAP ENGINEERED MULTI-GATE PMOS DEVICES Public/Granted day:2010-08-05
Information query
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