Invention Grant
US08169022B2 Vertical junction field effect transistors and diodes having graded doped regions and methods of making
有权
具有渐变掺杂区域的垂直结型场效应晶体管和二极管及其制造方法
- Patent Title: Vertical junction field effect transistors and diodes having graded doped regions and methods of making
- Patent Title (中): 具有渐变掺杂区域的垂直结型场效应晶体管和二极管及其制造方法
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Application No.: US12818232Application Date: 2010-06-18
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Publication No.: US08169022B2Publication Date: 2012-05-01
- Inventor: Lin Cheng , Michael Mazzola
- Applicant: Lin Cheng , Michael Mazzola
- Applicant Address: US MS Jackson
- Assignee: SS SC IP, LLC
- Current Assignee: SS SC IP, LLC
- Current Assignee Address: US MS Jackson
- Agency: Morris, Manning & Martin, LLP
- Agent Christopher W. Raimund
- Main IPC: H01L29/66
- IPC: H01L29/66
Abstract:
Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.
Public/Granted literature
- US20100320476A1 VERTICAL JUNCTION FIELD EFFECT TRANSISTORS AND DIODES HAVING GRADED DOPED REGIONS AND METHODS OF MAKING Public/Granted day:2010-12-23
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