Invention Grant
- Patent Title: Method of manufacturing a multilayer interconnection structure in a semiconductor device
- Patent Title (中): 在半导体器件中制造多层互连结构的方法
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Application No.: US12267970Application Date: 2008-11-10
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Publication No.: US08168532B2Publication Date: 2012-05-01
- Inventor: Masaki Haneda , Michie Sunayama , Noriyoshi Shimizu , Nobuyuki Ohtsuka , Yoshiyuki Nakao , Takahiro Tabira
- Applicant: Masaki Haneda , Michie Sunayama , Noriyoshi Shimizu , Nobuyuki Ohtsuka , Yoshiyuki Nakao , Takahiro Tabira
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2007-295778 20071114; JP2008-163798 20080623
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/538 ; H01L23/532

Abstract:
A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.
Public/Granted literature
- US20090121355A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2009-05-14
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