Packaging configurations for vertical electronic devices using conductive traces disposed on laminated board layers

Invention Grant

US08168477B2 Packaging configurations for vertical electronic devices using conductive traces disposed on laminated board layers 有权

Title translation: 使用布置在层压板层上的导电迹线的垂直电子设备的封装结构

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Patent Title: Packaging configurations for vertical electronic devices using conductive traces disposed on laminated board layers
Patent Title (中): 使用布置在层压板层上的导电迹线的垂直电子设备的封装结构
Application No.: US12927637

Application Date: 2010-11-18
Publication No.: US08168477B2

Publication Date: 2012-05-01
Inventor: Ming Sun , Yueh Se Ho
Applicant: Ming Sun , Yueh Se Ho
Applicant Address: US CA Sunnyvale
Assignee: Alpha and Omega Semiconductor Incorporated
Current Assignee: Alpha and Omega Semiconductor Incorporated
Current Assignee Address: US CA Sunnyvale
Agent Bo-In Lin
Main IPC: H01L21/50
IPC: H01L21/50

Packaging configurations for vertical electronic devices using conductive traces disposed on laminated board layers

Abstract:

This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.

Abstract(Chinese):

本发明公开了一种用于容纳垂直半导体芯片的电子封装件，该电子封装件包括具有通孔连接器的层压板和分布在连接到通孔连接器的叠层板的多层上的导电迹线。所述半导体芯片具有至少一个连接到所述导电迹线的电极，所述至少一个电极与所述层压板上的不同层上的所述导电迹线电连接，并且所述通孔连接器消散由所述垂直半导体产生的热量。连接到通孔连接器的球栅阵列（BGA），所述通孔连接器用作在封装的底表面处的接触件，用于安装在布置在印刷电路板（PCB）上的电端子上，其中所述层压板的热膨胀系数在基本相同的范围内该PCB由此使BGA与电气端子具有可靠的电接触。

Public/Granted literature

US20110076808A1 Packaging configurations for vertical electronic devices using conductive traces disposed on laminated board layers Public/Granted day:2011-03-31

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/50	...应用H01L21/06至H01L21/326中的任一小组都不包含的方法或设备组装半导体器件的