Invention Grant
US08149639B2 Test apparatus of semiconductor integrated circuit and method using the same 有权
半导体集成电路的测试装置及其使用方法

Test apparatus of semiconductor integrated circuit and method using the same
Abstract:
A test apparatus includes a test fuse unit for generating a test fuse signal in response to a test mode signal during a test time and generating a test fuse signals according to a fuse cutting after a termination of the test time, a combination signal generating unit for storing a test signal and inactivating a combination signal when the test mode signal is inactivate and for outputting the stored test signal as the combination signal when the test mode signal is activate, and a code signal generating unit for activating a test code signal when one of the test fuse signal and the combination signal is activated.
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