A method for stabilizing delay during conversion between Standard Definition (SD) video and High Definition (HD) video includes the step of establishing an integer divide ratio (M/N) corresponding to a ratio of clock rates with the output and input formats. The output clock rate is generated from the input clock rate by a Phase Lock Loop (104) using the M/N divide ratio to provide a known phase relationship between the two clocks rates at a repetitive interval. The video frame can be transferred at the known repetitive interval to provide coarse control over the input-to-output video delay. A separate fine tuning control (delay block) is provided to enable any programmable delay in video throughput to be accommodated to an accuracy of ±0.5 output pixel periods.