Invention Grant
- Patent Title: Low-noise voltage-controlled oscillating circuit
- Patent Title (中): 低噪声压控振荡电路
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Application No.: US12801421Application Date: 2010-06-08
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Publication No.: US08149069B2Publication Date: 2012-04-03
- Inventor: Yasuo Kitayama , Hiroyuki Demura
- Applicant: Yasuo Kitayama , Hiroyuki Demura
- Applicant Address: JP Tokyo
- Assignee: Nihon Dempa Kogyo Co., Ltd
- Current Assignee: Nihon Dempa Kogyo Co., Ltd
- Current Assignee Address: JP Tokyo
- Agency: Jacobson Holman PLLC
- Priority: JPP.2009-137114 20090608
- Main IPC: H03B5/08
- IPC: H03B5/08

Abstract:
A low noise voltage-controlled oscillating circuit which can remove a power source noise to improve low frequency noise characteristics is disclosed. A capacitor C11 is provided between a base of a driving transistor Q1 and GND, whereby a low frequency noise input into the base can be removed. As the driving transistor Q1, a transistor having a low hFE is used, whereby the low frequency noise input from a power source can be removed. A coil L3 is provided on the emitter side of an oscillating transistor Q2, whereby broadband frequency characteristics can be obtained to improve phase noise frequency characteristics. On the emitter side of the oscillating transistor Q2, a resonance frequency in a resonant circuit having a capacitor C7 and the coil L3 is set near the center of a VCO oscillation frequency band, whereby it is possible to obtain the oscillation frequency which is not easily influenced by the noise.
Public/Granted literature
- US20100308929A1 Low-noise voltage-controlled oscillating circuit Public/Granted day:2010-12-09
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