Invention Grant
- Patent Title: Method of forming isolation layer of semiconductor memory device
- Patent Title (中): 形成半导体存储器件隔离层的方法
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Application No.: US12137380Application Date: 2008-06-11
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Publication No.: US08148267B2Publication Date: 2012-04-03
- Inventor: Whee Won Cho , Jong Hye Cho
- Applicant: Whee Won Cho , Jong Hye Cho
- Applicant Address: KR Icheon-si
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Icheon-si
- Agency: Marshall, Gerstein & Borun LLP
- Priority: KR10-2007-0140285 20071228
- Main IPC: H01L21/302
- IPC: H01L21/302 ; H01L21/461 ; H01L21/311

Abstract:
A method of forming isolation layers of a semiconductor memory device. In accordance with an embodiment of the invention, a semiconductor substrate in which trenches are formed is provided. A first dielectric layer is formed over the semiconductor substrate including the trenches. An opening width of the trench is widened by performing a first etch process to remove a part of the first dielectric layer, followed by an annealing process. Fluorine-containing impurities formed in the first dielectric layer as a result of the etching and annealing processes are removed by performing a second etch process. A second dielectric layer is formed over the semiconductor substrate including the first dielectric layer.
Public/Granted literature
- US20090170321A1 Method of Forming Isolation Layer of Semiconductor Memory Device Public/Granted day:2009-07-02
Information query
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