Invention Grant
- Patent Title: Method for assembling a wafer level test probe card
- Patent Title (中): 组装晶圆级测试探针卡的方法
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Application No.: US12787560Application Date: 2010-05-26
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Publication No.: US08146245B2Publication Date: 2012-04-03
- Inventor: Clinton Chih-Chieh Chao , Fei-Chieh Yang , Chun-Hsing Chen , Mill-Jer Wang , Sheng-Hsi Huang , Ming-Cheng Hsu
- Applicant: Clinton Chih-Chieh Chao , Fei-Chieh Yang , Chun-Hsing Chen , Mill-Jer Wang , Sheng-Hsi Huang , Ming-Cheng Hsu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Agent Frank J. Spanitz
- Main IPC: H05K3/34
- IPC: H05K3/34 ; H05K3/30 ; H05K1/16 ; G01R31/20

Abstract:
A method for assembling a probe card for wafer level testing of a plurality of semiconductor devices simultaneously is disclosed. The probe card may include a circuit board including wafer level testing circuitry, a partially flexible silicon substrate, a plurality of test probes disposed at least partially in the substrate for engaging a plurality of corresponding electrical contacts in a wafer under test, and a compressible underfill coupling the substrate to the circuit board. The method includes aligning and assembling the foregoing components, and curing the underfill. The probe card may be used for wafer level burn-in testing. In some embodiments, the probe card may include active test control circuitry embedded in the silicon substrate for conducting wafer level high frequency testing.
Public/Granted literature
- US20100229383A1 WAFER LEVEL TEST PROBE CARD Public/Granted day:2010-09-16
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