Invention Grant
- Patent Title: Semiconductor device having delay control circuit
- Patent Title (中): 具有延迟控制电路的半导体装置
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Application No.: US12588200Application Date: 2009-10-07
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Publication No.: US08134877B2Publication Date: 2012-03-13
- Inventor: Kyoichi Nagata
- Applicant: Kyoichi Nagata
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2008-261805 20081008
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
A first delay circuit and a second delay circuit having different operation conditions from each other, a detection circuit that detects a difference in propagation speed of a pulse signal, which is simultaneously input to the first and second delay circuits, and a setting circuit that generates a selection signal based on a detection result from the detection circuit are provided. The selection signal is supplied to a delay control circuit that generates an operation timing signal by delaying a reference signal, of which a delay amount is controlled by the selection signal. With this arrangement, a necessity to set the delay amount of the delay control circuit with a large design margin can be eliminated considering PVT variation, and as a result, performance degradation can be prevented.
Public/Granted literature
- US20100085824A1 Semiconductor device having delay control circuit Public/Granted day:2010-04-08
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