Invention Grant
US08134871B2 Programming memory with reduced pass voltage disturb and floating gate-to-control gate leakage
有权
编程存储器具有降低的通过电压干扰和浮动栅极到控制栅极泄漏
- Patent Title: Programming memory with reduced pass voltage disturb and floating gate-to-control gate leakage
- Patent Title (中): 编程存储器具有降低的通过电压干扰和浮动栅极到控制栅极泄漏
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Application No.: US12536127Application Date: 2009-08-05
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Publication No.: US08134871B2Publication Date: 2012-03-13
- Inventor: Deepanshu Dutta , Henry Chin
- Applicant: Deepanshu Dutta , Henry Chin
- Applicant Address: US TX Plano
- Assignee: SanDisk Technologies Inc.
- Current Assignee: SanDisk Technologies Inc.
- Current Assignee Address: US TX Plano
- Agency: Vierra Magen Marcus & DeNiro LLP
- Main IPC: G11C16/04
- IPC: G11C16/04
Abstract:
Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn−1 neighbor storage element, and applying an optimal pass voltage to WLn−1 for each group. Initially, the states of the storage elements on WLn−1 are read. A program iteration includes multiple program pulses. A first program pulse is applied to WLn while a first pass voltage is applied to WLn−1, a first group of WLn storage elements is selected for programming, and a second group of WLn storage elements is inhibited. Next, a second program pulse is applied to WLn while a second pass voltage is applied to WLn−1, the second first group of WLn storage elements is selected for programming, and the first group of WLn storage elements is inhibited. A group can include one or more data states.
Public/Granted literature
- US20110032757A1 Programming Memory With Reduced Pass Voltage Disturb And Floating Gate-To-Control Gate Leakage Public/Granted day:2011-02-10
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