Invention Grant
- Patent Title: Memory device biasing method and apparatus
- Patent Title (中): 存储器件偏置方法和装置
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Application No.: US12265989Application Date: 2008-11-06
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Publication No.: US08134868B2Publication Date: 2012-03-13
- Inventor: Uday Chandrasekhar
- Applicant: Uday Chandrasekhar
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Leffert Jay & Polglaze, P.A.
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory string source line. For example, alternating data lines are sensed while adjacent data lines are coupled to a common source line of the data lines being sensed. Data line shielding methods and apparatus disclosed can reduce effects of source line bounce occurring during a sense operation of a memory device.
Public/Granted literature
- US20100110789A1 MEMORY DEVICE BIASING METHOD AND APPARATUS Public/Granted day:2010-05-06
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