Invention Grant
- Patent Title: Nanowire transistor with surrounding gate
- Patent Title (中): 纳米线晶体管与周边门
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Application No.: US12192618Application Date: 2008-08-15
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Publication No.: US08134197B2Publication Date: 2012-03-13
- Inventor: Leonard Forbes
- Applicant: Leonard Forbes
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: H01L21/331
- IPC: H01L21/331

Abstract:
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.
Public/Granted literature
- US20080315279A1 NANOWIRE TRANSISTOR WITH SURROUNDING GATE Public/Granted day:2008-12-25
Information query
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