Invention Grant
US08132133B2 Automated isolation of logic and macro blocks in chip design testing
有权
在芯片设计测试中自动隔离逻辑和宏块
- Patent Title: Automated isolation of logic and macro blocks in chip design testing
- Patent Title (中): 在芯片设计测试中自动隔离逻辑和宏块
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Application No.: US12196840Application Date: 2008-08-22
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Publication No.: US08132133B2Publication Date: 2012-03-06
- Inventor: Animesh Khare , Narendra Keshav Rane
- Applicant: Animesh Khare , Narendra Keshav Rane
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Grant A. Johnson; Roy W. Truelson
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A method and system for testing a synthesized design of a semiconductor chip. The method includes inputting a macro test Input/Output (I/O) name of the semiconductor chip, along with associated attributes and a netlist, where the netlist is a synthesized design of the semiconductor chip. The method includes tracking the macro test I/O to a chip test I/O. The method further includes detecting mismatches between attributes associated with the macro test I/O and the chip test I/O. Subsequently, reporting any mismatches between the attributes associated with the macro test I/O and the chip test I/O.
Public/Granted literature
- US20100050137A1 AUTOMATED ISOLATION OF LOGIC AND MACRO BLOCKS IN CHIP DESIGN TESTING Public/Granted day:2010-02-25
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