A processor and cache is coupled to a system memory via a system interconnect. A first buffer circuit coupled to the cache receives one or more data words and stores the one or more data words in each of one or more entries. The one or more data words of a first entry are written to the cache in response to error free receipt. A second buffer circuit coupled to the cache has one or more entries for storing store requests. Each entry has an associated control bit that determines whether an entry formed from a first store request is a valid entry to be written to the system memory from the second buffer circuit. Based upon error free receipt of the one or more data words, the associated control bit is set to a value that invalidates the entry in the second buffer circuit based upon the error determination.