Invention Grant
US08131943B2 Structure for dynamic initial cache line coherency state assignment in multi-processor systems
有权
多处理器系统中动态初始高速缓存行一致性状态分配的结构
- Patent Title: Structure for dynamic initial cache line coherency state assignment in multi-processor systems
- Patent Title (中): 多处理器系统中动态初始高速缓存行一致性状态分配的结构
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Application No.: US12114788Application Date: 2008-05-04
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Publication No.: US08131943B2Publication Date: 2012-03-06
- Inventor: Daniel J. Colglazier , Marcus L. Kornegay , Ngan N. Pham , Cristian G. Rojas
- Applicant: Daniel J. Colglazier , Marcus L. Kornegay , Ngan N. Pham , Cristian G. Rojas
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Patterson & Sheridan LLP
- Main IPC: G06F12/00
- IPC: G06F12/00

Abstract:
A design structure embodied in a machine readable storage medium for designing, manufacturing, and testing a system for providing lines of data from shared resources to caching agents are provided. The system provides for receiving a request from a caching agent for a line of data stored in a shared resource, assigning one of a plurality of coherency states as an initial coherency state for the line of data, each of the plurality of coherency states being assignable as the initial coherency state for the line of data, and providing the line of data to the caching agent in the initial coherency state assigned to the line of data.
Public/Granted literature
- US20090019233A1 STRUCTURE FOR DYNAMIC INITIAL CACHE LINE COHERENCY STATE ASSIGNMENT IN MULTI-PROCESSOR SYSTEMS Public/Granted day:2009-01-15
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