Invention Grant
US08131531B2 System and method for simulating a semiconductor wafer prober and a class memory test handler
有权
用于模拟半导体晶圆探测器和类别存储器测试处理器的系统和方法
- Patent Title: System and method for simulating a semiconductor wafer prober and a class memory test handler
- Patent Title (中): 用于模拟半导体晶圆探测器和类别存储器测试处理器的系统和方法
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Application No.: US11998481Application Date: 2007-11-30
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Publication No.: US08131531B2Publication Date: 2012-03-06
- Inventor: Larry Ira Goldsmith
- Applicant: Larry Ira Goldsmith
- Applicant Address: SG Singapore
- Assignee: Verigy (Singapore) Pte. Ltd.
- Current Assignee: Verigy (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Holland & Hart, LLP
- Main IPC: G06F9/44
- IPC: G06F9/44 ; G06F13/10 ; G06F13/12
Abstract:
A method runs a simulation. The method comprises receiving a selection of a device. The device is one of a prober used in wafer testing and a handler used in package testing. The method comprises receiving at least one parameter for a set of parameters for the simulation. The method comprises running the simulation by executing commands to be performed as if the device were present. A controller supplies the set of commands. Results from the simulation indicate a performance of the controller.
Public/Granted literature
- US20090144041A1 System and method for simulating a semiconductor wafer prober and a class memory test handler Public/Granted day:2009-06-04
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