Invention Grant
US08130127B1 Discrete-time delta-sigma modulator with improved anti-aliasing at lower quantization rates 有权
离散时间Δ-Σ调制器,在较低量化速率下具有改进的抗锯齿

Discrete-time delta-sigma modulator with improved anti-aliasing at lower quantization rates
Abstract:
A discrete time delta-sigma modulator circuit, which may be used to implement an analog-to-digital converter (ADC) provides improved anti-aliasing performance when lower quantization rates are selected, by maintaining the clocking rate of a first stage in the delta-sigma modulator loop filter at a rate higher than would ordinarily be selected for a lower quantization rate. To accomplish the anti-aliasing improvement, the ratio between the quantization rate and the clocking rate of the first integrator is reduced at the lower quantization rate, resulting in a first true alias image at a multiple of the quantization rate, permitting anti-aliasing filters to more effectively attenuate the alias image, and attenuating the images spaced at the quantization rate via the averaging operation of the first integrator.
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