Invention Grant
- Patent Title: Electronic device package structures
- Patent Title (中): 电子器件封装结构
-
Application No.: US11184166Application Date: 2005-07-19
-
Publication No.: US08129839B2Publication Date: 2012-03-06
- Inventor: Warren M. Farnworth
- Applicant: Warren M. Farnworth
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A sealing layer is provided on a surface of a substrate, such as a semiconductor wafer. The sealing layer includes apertures which expose external contact locations for semiconductor dice formed on the wafer. Solder paste is deposited in the apertures and reflowed to form discrete conductive elements for attachment of electronic devices to higher level circuit structures. The wafer is then divided or “singulated” to provide individual semiconductor dice having their active surfaces covered by the sealing layer. In this manner, the sealing layer initially acts as a stencil for forming the discrete conductive elements and subsequently forms a chip scale package structure to protect the semiconductor dice from the environment.
Public/Granted literature
- US20050253261A1 Electronic device package structures Public/Granted day:2005-11-17
Information query
IPC分类: