Invention Grant
- Patent Title: IC chip package employing substrate with a device hole
- Patent Title (中): IC芯片封装采用具有器件孔的衬底
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Application No.: US12312981Application Date: 2007-11-30
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Publication No.: US08129825B2Publication Date: 2012-03-06
- Inventor: Satoru Kudose , Tomokatsu Nakagawa , Tatsuya Katoh
- Applicant: Satoru Kudose , Tomokatsu Nakagawa , Tatsuya Katoh
- Applicant Address: JP Osaka
- Assignee: Sharp Kabushiki Kaisha
- Current Assignee: Sharp Kabushiki Kaisha
- Current Assignee Address: JP Osaka
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: JP2006-329993 20061206
- International Application: PCT/JP2007/073189 WO 20071130
- International Announcement: WO2008/069135 WO 20080612
- Main IPC: H01L23/495
- IPC: H01L23/495
Abstract:
In one embodiment of the present invention, an IC chip mounting package includes a film base member and an IC chip connected via an interposer. Connecting terminals on the film base member side of the interposer are provided so as to have a pitch larger than that of connecting terminals of the IC. A device hole is opened to the film base member, and the IC chip is provided in the device hole. A distance between an inner lead leading end and a periphery of the device hole is set as not less than 10 μm.
Public/Granted literature
- US20100019394A1 IC CHIP MOUNTING PACKAGE Public/Granted day:2010-01-28
Information query
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