Invention Grant
US08129753B2 Integrated circuit including gate electrode level region including at least seven linear-shaped conductive structures of equal length positioned at equal pitch with at least two linear-shaped conductive structures each forming one transistor and having extending portion sized greater than gate portion 有权
集成电路,包括栅电极电平区域,包括至少七个相等长度的直线形导电结构,其等同距离与至少两个线形导电结构形成,每个形成一个晶体管,并具有尺寸大于栅极部分的延伸部分

  • Patent Title: Integrated circuit including gate electrode level region including at least seven linear-shaped conductive structures of equal length positioned at equal pitch with at least two linear-shaped conductive structures each forming one transistor and having extending portion sized greater than gate portion
  • Patent Title (中): 集成电路,包括栅电极电平区域,包括至少七个相等长度的直线形导电结构,其等同距离与至少两个线形导电结构形成,每个形成一个晶体管,并具有尺寸大于栅极部分的延伸部分
  • Application No.: US12567648
    Application Date: 2009-09-25
  • Publication No.: US08129753B2
    Publication Date: 2012-03-06
  • Inventor: Scott T. BeckerMichael C. Smayling
  • Applicant: Scott T. BeckerMichael C. Smayling
  • Applicant Address: US CA Los Gatos
  • Assignee: Tela Innovations, Inc.
  • Current Assignee: Tela Innovations, Inc.
  • Current Assignee Address: US CA Los Gatos
  • Agency: Martine Penilla Group, LLP
  • Main IPC: H01L27/10
  • IPC: H01L27/10
Integrated circuit including gate electrode level region including at least seven linear-shaped conductive structures of equal length positioned at equal pitch with at least two linear-shaped conductive structures each forming one transistor and having extending portion sized greater than gate portion
Abstract:
A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions. The layout of the cell also includes a gate electrode level layout defined to include a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight.
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