Invention Grant
US08129258B2 Method for dicing a semiconductor wafer, a chip diced from a semiconductor wafer, and an array of chips diced from a semiconductor wafer
有权
用于切割半导体晶片的方法，从半导体晶片切割的芯片以及从半导体晶片切割的芯片阵列
- Patent Title: Method for dicing a semiconductor wafer, a chip diced from a semiconductor wafer, and an array of chips diced from a semiconductor wafer
- Patent Title (中): 用于切割半导体晶片的方法，从半导体晶片切割的芯片以及从半导体晶片切割的芯片阵列
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Application No.: US12646590Application Date: 2009-12-23
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Publication No.: US08129258B2Publication Date: 2012-03-06
- Inventor: Paul A. Hosier , Nicholas J. Salatino
- Applicant: Paul A. Hosier , Nicholas J. Salatino
- Applicant Address: US CT Norwalk
- Assignee: Xerox Corporation
- Current Assignee: Xerox Corporation
- Current Assignee Address: US CT Norwalk
- Agency: Simpson & Simpson, PLLC
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
A method for dicing a semiconductor wafer, including: cutting a reference slot in a back main surface of the wafer; cutting a back slot in the back main surface, the back slot positioned with respect to the reference slot; determining a desired location for a chip edge with respect to the reference slot; and applying radiant energy in a path such that a series of reformed regions are formed within the wafer along the path. A crystalline structure of the wafer is modified in the series of reformed regions and an alignment of an edge of the laser is with respect to the desired location for the chip edge and in alignment with the back slot. The method includes separating the wafer along the series of reformed regions to divide portions of the wafer on either side of the series of reformed regions.
Public/Granted literature
Information query
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