Invention Grant
- Patent Title: Processor with enhanced combined-arithmetic capability
- Patent Title (中): 具有增强的组合算术能力的处理器
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Application No.: US11973887Application Date: 2007-10-09
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Publication No.: US08122078B2Publication Date: 2012-02-21
- Inventor: Brucek Khailany , William James Dally , Raghunath Rao , DeForest Tovey
- Applicant: Brucek Khailany , William James Dally , Raghunath Rao , DeForest Tovey
- Applicant Address: US DE Dover
- Assignee: Calos Fund, LLC
- Current Assignee: Calos Fund, LLC
- Current Assignee Address: US DE Dover
- Main IPC: G06F15/00
- IPC: G06F15/00

Abstract:
A method of operation within an integrated-circuit processing device having an enhanced combined-arithmetic capability. In response to an instruction indicating a combined arithmetic operation, the processor generates a dot-product of first and second operands, adds the dot-product to an accumulated value, and then outputs the sum of the accumulated value and the dot-product.
Public/Granted literature
- US20080140994A1 Data-Parallel processing unit Public/Granted day:2008-06-12
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