Invention Grant
- Patent Title: Multi-level LVDS data transmission with embedded word clock
- Patent Title (中): 具有嵌入式字时钟的多级LVDS数据传输
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Application No.: US11746610Application Date: 2007-05-09
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Publication No.: US08121200B2Publication Date: 2012-02-21
- Inventor: Dong Zheng
- Applicant: Dong Zheng
- Applicant Address: US CA Milpitas
- Assignee: Intersil Americas Inc.
- Current Assignee: Intersil Americas Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Fogg & Powers LLC
- Main IPC: H04B14/04
- IPC: H04B14/04

Abstract:
A multi-level signal uses the third/fourth signal level to signal both a word clock edge and a data word boundary. At the receiver, a level detector detects a transition to or from the third/fourth level as a clock signal transition and the word boundary. The bit clock can be recovered using a conventional clock multiplier. Bi-level signaling is used for data between the word boundaries. Additional signal states are available in the multi-level signal by modulating the pulse width at the third/fourth signal level.
Public/Granted literature
- US20080012746A1 MULTI-LEVEL LVDS DATA TRANSMISSION WITH EMBEDDED WORD CLOCK Public/Granted day:2008-01-17
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