Invention Grant
US08120887B2 MOS transistor triggered transient voltage suppressor to provide circuit protection at a lower voltage 有权
MOS晶体管触发瞬态电压抑制器以在较低电压下提供电路保护

MOS transistor triggered transient voltage suppressor to provide circuit protection at a lower voltage
Abstract:
An electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering MOS transistor connected between an emitter and a collector of a first bipolar-junction transistor (BJT) coupled to a second BJT to form a SCR functioning as a main clamp circuit of the TVS circuit. The TVS circuit further includes a triggering circuit for generating a triggering signal for the triggering MOS transistor wherein the triggering circuit includes multiple stacked MOS transistors for turning into a conductive state by a transient voltage while maintaining a low leakage current.
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