Invention Grant
US08120887B2 MOS transistor triggered transient voltage suppressor to provide circuit protection at a lower voltage
有权
MOS晶体管触发瞬态电压抑制器以在较低电压下提供电路保护
- Patent Title: MOS transistor triggered transient voltage suppressor to provide circuit protection at a lower voltage
- Patent Title (中): MOS晶体管触发瞬态电压抑制器以在较低电压下提供电路保护
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Application No.: US11712317Application Date: 2007-02-28
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Publication No.: US08120887B2Publication Date: 2012-02-21
- Inventor: Shekar Mallikararjunaswamy , Madhur Bobde
- Applicant: Shekar Mallikararjunaswamy , Madhur Bobde
- Applicant Address: BM
- Assignee: Alpha & Omega Semiconductor, Ltd.
- Current Assignee: Alpha & Omega Semiconductor, Ltd.
- Current Assignee Address: BM
- Agency: Bo-InLin
- Main IPC: H02H3/22
- IPC: H02H3/22 ; H02H9/00

Abstract:
An electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering MOS transistor connected between an emitter and a collector of a first bipolar-junction transistor (BJT) coupled to a second BJT to form a SCR functioning as a main clamp circuit of the TVS circuit. The TVS circuit further includes a triggering circuit for generating a triggering signal for the triggering MOS transistor wherein the triggering circuit includes multiple stacked MOS transistors for turning into a conductive state by a transient voltage while maintaining a low leakage current.
Public/Granted literature
- US20080218922A1 MOS transistor triggered transient voltage supressor to provide circuit protection at a lower voltage Public/Granted day:2008-09-11
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