Invention Grant
- Patent Title: Delay locked loop circuit
- Patent Title (中): 延时锁定回路电路
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Application No.: US12844620Application Date: 2010-07-27
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Publication No.: US08120396B2Publication Date: 2012-02-21
- Inventor: Masaaki Iwane
- Applicant: Masaaki Iwane
- Applicant Address: JP Tokyo
- Assignee: Canon Kabushiki Kaisha
- Current Assignee: Canon Kabushiki Kaisha
- Current Assignee Address: JP Tokyo
- Agency: Fitzpatrick, Cella, Harper & Scinto
- Priority: JP2009-181966 20090804; JP2010-165346 20100722
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A delay locked loop circuit comprising a VCDL which outputs a feedback clock by delaying an input clock in accordance with a magnitude of a control voltage, a phase comparator which detects a phase difference between the feedback clock and a reference clock by comparing the feedback clock with the reference clock, and outputs an Up-signal for raising the control voltage and a Down-signal for lowering the control voltage in accordance with the phase difference, a control voltage generation circuit which determines the control voltage in accordance with the Up-signal and the Down-signal, and outputs the control voltage to the VCDL, and a reset circuit which resets the phase comparator based on a logical OR between the reference clock and a first intermediate clock which is a signal obtained by delaying the input clock by the VCDL and is output before the feedback clock.
Public/Granted literature
- US20110032009A1 DELAY LOCKED LOOP CIRCUIT Public/Granted day:2011-02-10
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