Invention Grant
- Patent Title: Phase-locked loop system with a phase-error spreading circuit
- Patent Title (中): 具有相位误差扩展电路的锁相环系统
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Application No.: US12180166Application Date: 2008-07-25
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Publication No.: US08094769B2Publication Date: 2012-01-10
- Inventor: Gayathri A. Bhagavatheeswaran , Lipeng Cao , Hector Sanchez
- Applicant: Gayathri A. Bhagavatheeswaran , Lipeng Cao , Hector Sanchez
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Charles Bergere
- Main IPC: H03D3/24
- IPC: H03D3/24

Abstract:
A phase-locked loop (PLL) system including a phase-frequency detector for generating an up signal or a down signal based on a phase difference between a reference clock and a feedback clock is provided. The PLL system further includes a phase-error spreading circuit for generating phase-spread pulses based on a relationship between a first time attribute of the up signal or the down signal and a second time attribute of the phase-spread pulses. The PLL system further includes a voltage-controlled oscillator (VCO) for generating a VCO clock based on the phase-spread pulses. The PLL system may also include a charge pump that generates a pumping signal based on the phase-spread pulses.
Public/Granted literature
- US20100020910A1 PHASE-LOCKED LOOP SYSTEM WITH A PHASE-ERROR SPREADING CIRCUIT Public/Granted day:2010-01-28
Information query
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