Invention Grant
US08094677B2 Multi-bus structure for optimizing system performance of a serial buffer
有权
多总线结构,用于优化串行缓冲器的系统性能
- Patent Title: Multi-bus structure for optimizing system performance of a serial buffer
- Patent Title (中): 多总线结构,用于优化串行缓冲器的系统性能
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Application No.: US11679824Application Date: 2007-02-27
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Publication No.: US08094677B2Publication Date: 2012-01-10
- Inventor: Steve Juan , Chi-Lie Wang , Ming-Shiung Chen
- Applicant: Steve Juan , Chi-Lie Wang , Ming-Shiung Chen
- Applicant Address: US CA San Jose
- Assignee: Integrated Device Technology, Inc.
- Current Assignee: Integrated Device Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Bever, Hoffman & Harms LLP
- Main IPC: H04J3/16
- IPC: H04J3/16

Abstract:
A serial buffer having a parser and multiple parallel processing paths is provided. The parser receives incoming packets, determines the type of each packet, and then routes each packet to a processing path that corresponds with the determined packet type. Packet types may include blocking priority packets (which implement bus slave operations), non-blocking priority packets (which access on-chip resources of the serial buffer) and data packets (which implement bus master operations). Because the different packet types are processed on parallel processing paths, the processing of one packet type does not interfere with the processing of other packet types. As a result, blocking conditions within the serial buffer are minimized.
Public/Granted literature
- US20080205438A1 Multi-Bus Structure For Optimizing System Performance Of a Serial Buffer Public/Granted day:2008-08-28
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