A memory includes ferroelectric capacitors; sense amplifiers configured to detect the data stored in ferroelectric capacitors; and a plate control circuit configured to receive a plate driving signal driving a plate line, a write signal indicating writing of data from an outside to the sense amplifier, and an operation end signal indicating end of an executable period for reading or writing data between the sense amplifier and the outside, the plate control circuit validating or invalidating the plate driving signal based on the write signal and the operation end signal wherein the plate control circuit validates the plate driving signal in the executable period, and the plate control circuit invalidates the plate driving signal at the end of the executable period when the write signal is never activated in the executable period, and keeps the plate driving signal valid when the write signal is activated in the executable period.