Invention Grant
- Patent Title: Chip assembly with chip-scale packaging
- Patent Title (中): 芯片组装采用芯片级封装
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Application No.: US12635677Application Date: 2009-12-10
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Publication No.: US08093714B2Publication Date: 2012-01-10
- Inventor: Andrew J. Bonthron , Darren Jay Walworth
- Applicant: Andrew J. Bonthron , Darren Jay Walworth
- Applicant Address: US CA Camarillo
- Assignee: Semtech Corporation
- Current Assignee: Semtech Corporation
- Current Assignee Address: US CA Camarillo
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L23/34
- IPC: H01L23/34

Abstract:
A chip assembly may comprise a substrate having a top surface and a bottom surface. The chip assembly may comprise a first die having a circuit surface and a connecting surface, the circuit surface comprising one or more integrated circuits. The chip assembly may comprise a chip-scale frame having an inside surface, an outside surface, and a well region, the well region having an opening within the inside surface, the well region having a wall, the well region housing the first die, the first die attached to the wall by a first coupling mechanism, the inside surface coupled to the top surface of the substrate by a second coupling mechanism. The chip assembly may comprise a heat sink coupled to the outside surface of the chip-scale frame using a third coupling mechanism.
Public/Granted literature
- US20110140260A1 CHIP ASSEMBLY WITH CHIP-SCALE PACKAGING Public/Granted day:2011-06-16
Information query
IPC分类: