Invention Grant
US08093647B2 Nonvolatile semiconductor memory having transistor with a diffusion blocking layer between the lower gate and fully silicided upper gate
失效
非易失性半导体存储器具有在下栅极和完全硅化的上栅极之间具有扩散阻挡层的晶体管
- Patent Title: Nonvolatile semiconductor memory having transistor with a diffusion blocking layer between the lower gate and fully silicided upper gate
- Patent Title (中): 非易失性半导体存储器具有在下栅极和完全硅化的上栅极之间具有扩散阻挡层的晶体管
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Application No.: US11959919Application Date: 2007-12-19
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Publication No.: US08093647B2Publication Date: 2012-01-10
- Inventor: Atsuhiro Sato , Mutsumi Okajima
- Applicant: Atsuhiro Sato , Mutsumi Okajima
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2006-343169 20061220
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/788 ; H01L29/78 ; H01L23/52 ; H01L29/40 ; H01L29/49
Abstract:
A memory cell has a floating gate electrode, a first inter-gate insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the first inter-gate insulating film. An FET has a lower gate electrode, a second inter-gate insulating film having an opening and arranged on the lower gate electrode, a block film having a function to block diffusion of metal atoms and formed on at least the opening, and an upper gate electrode connected electrically to the lower gate electrode via the block film and arranged on the second inter-gate insulating film. The control gate electrode and the upper gate electrode have a Full-silicide structure.
Public/Granted literature
- US20080179654A1 NONVOLATILE SEMICONDUCTOR MEMORY Public/Granted day:2008-07-31
Information query
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