A memory-specific tester has a buffer storing input pattern data and output expectation data. An address included in the input pattern data read from the buffer is sent to a semiconductor memory, and is then subjected to descrambling at a security circuit. The descrambled address is converted at an address conversion circuit to an address designating a region for storing a check pattern in a memory core. Data given from the memory core (check pattern) is subjected to scrambling at the security circuit, and is then sent to the memory-specific tester. The memory-specific tester makes comparison between expectation data and the data read from the semiconductor memory.