Invention Grant
US08090913B2 Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memory
有权
串行耦合处理核心的一致性组将包含写入包的一致性信息传播到存储器
- Patent Title: Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memory
- Patent Title (中): 串行耦合处理核心的一致性组将包含写入包的一致性信息传播到存储器
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Application No.: US12972878Application Date: 2010-12-20
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Publication No.: US08090913B2Publication Date: 2012-01-03
- Inventor: Perry H. Pelley, III , George P. Hoekstra , Lucio F. Pessoa
- Applicant: Perry H. Pelley, III , George P. Hoekstra , Lucio F. Pessoa
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent James L. Clingan, Jr.; David G. Dolezal; Jonathan N. Geld
- Main IPC: G06F12/08
- IPC: G06F12/08
Abstract:
A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet switch. The packet switch is coupled to a memory. The first plurality of cores and the packet switch are on an integrated circuit. The memory may or may not be on the integrated circuit. In another aspect a second plurality of cores in a second coherency group is coupled to the packet switch. The cores of the first and second pluralities may be reconfigured to form or become part of coherency groups different from the first and second coherency groups.
Public/Granted literature
- US20110093660A1 MULTI-CORE PROCESSING SYSTEM Public/Granted day:2011-04-21
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