Invention Grant
US08090758B1 Enhanced multiplier-accumulator logic for a programmable logic device
有权
用于可编程逻辑器件的增强型乘法器累加器逻辑
- Patent Title: Enhanced multiplier-accumulator logic for a programmable logic device
- Patent Title (中): 用于可编程逻辑器件的增强型乘法器累加器逻辑
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Application No.: US11639994Application Date: 2006-12-14
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Publication No.: US08090758B1Publication Date: 2012-01-03
- Inventor: Schuyler E. Shimanek , William E. Allaire , Steven J. Zack
- Applicant: Schuyler E. Shimanek , William E. Allaire , Steven J. Zack
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agent Robert M. Brush; LeRoy D. Maunu; Lois D. Cartier
- Main IPC: G06F7/38
- IPC: G06F7/38

Abstract:
A multiplier-accumulator includes a pre-adder, a multiplier, an accumulator, multiplexing logic, and control logic. The pre-adder is configured to sum a first input and a second input to produce a pre-sum output. The multiplier is configured to multiply a third input and the pre-sum output to produce a product output. The accumulator is configured to sum a pair of accumulator inputs to produce a sum output. The multiplexer is configured to select the pair of accumulator inputs from a plurality of multiplexer inputs, where the plurality of multiplexer inputs includes the product output and the sum output. The control logic is configured to control operation of the pre-adder, the accumulator, and the multiplexer logic. In an example, each of the first input, the second input, the third input, and the sum output is coupled to programmable interconnect of a programmable logic device.
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